1. Field of the Invention
The present invention relates in general to computer memories, currently referred to as main memories used in central processing units. More particularly, the present invention relates to a modular memory for use in a high performance computer system employing, for example, vector processors. Modular memories in accordance with the present invention may be in the form of semiconductor memories, such as static storage memories.
2. Background Discussion
A central processing unit is generally comprised of one or more processors connected to a main memory via a memory controller. The processors normally access data contained in the memory by sending commands to the memory controller in the form of command signals (read or write commands), address signals and data signals, in the case of a write command. The command signals are generally preceded or accompanied by a request signal that alerts the memory controller that a request has been sent.
In response to such a request, the memory controller then performs a series of operations that include loading the request parameters into an input register. Generally, the memory controller also sends acknowledgement signals to inform the processor that the request has been accepted, and then that the response is available in the memory controller's output register.
The response includes data contained in the address furnished by the processor in the case of a read operation. The response can also include an error report to inform the processor whether the operation requested has been performed correctly.
The basic parameters for evaluating the performance of a memory are access time and cycle time. Access time is defined as being the amount of time between the sending of a request by the processor and the appearance of an acknowledgement signal indicating that the request has been retrieved by the memory, thus indicating that a new request can be sent to the memory by the processor. Cycle time defines the time between when a request is received by the memory and the time when the response is available in the memory's output register.
The way computers are presently designed, memories have increasingly large capacities. On the other hand, they are trying to make processors with increasingly higher performance, that is, with more memory access per second. Various techniques are used to increase processor performance, such as using multiprocessor systems and/or so-called "pipeline" architecture.
However, to make good use of the progress made in processors, it is also desirable for the performance of the memories to be compatible. Memories are therefore designed with the shortest possible access and cycle times. But these conditions are difficult to reconcile with an increase in memory capacity since, with the present technology, a memory's access time increases with its capacity.
To resolve this problem, one classic solution is to use a memory composed of several modules, with each module consequently having an access time that is lower than that of a nonmodular memory with the same capacity. Also, an interlacing technique, where successive requests sent by the processors are addressed to different memory modules in succession, is being used.
However, this solution poses another problem, which is that of the connections between the processors and the various memory modules. One method that is already known uses different access paths for each of the modules. A processor is then connected to modules via an interconnecting circuit with as much connection as the memory has modules. In the case of a multiprocessor system, such as a vector processor, the interconnecting circuit functions just like a "crossbar" system. This method has the advantage of authorizing some simultaneous access by the processors with several memory modules. However, this solution is limited to cases where the number of modules and processors is relatively small. In fact, beyond about ten modules, the interconnection device becomes difficult to design and control. Moreover, it entails increasing the system's cycle time.
Another known solution avoids this drawback by using a bus-type connection between the processors and the different modules. In this case, one memory controller per module is specified, and each controller is supplied with an input register and an address decoder. Usually, two separate busses are used to transport commands and responses so that, in the interlaced mode, the total memory access time is equal to the access time of one module divided by the number of modules.
However, this last solution has the following disadvantage. The response to a request addressed to any module whatsoever in the memory is available in the output register of the module at the end of a period of time that corresponds to the time that the processor sends the request to the module plus the cycle time of the module. Now, the sending time and the cycle time can vary from one module to another. These differences become quite considerable when the processor's cycle time decreases and the number of modules increases, for then the responses to two successive commands addressed to two different modules can appear simultaneously on the output bus.
Accordingly, it is an object of the present invention to eliminate the aforementioned disadvantages by ensuring that the responses coming from the different modules are received in succession by the processor in an order substantially identical to the order in which the corresponding requests were made and accepted by the modules.